Wafer Service Overview
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In electronics, a wafer is a thin slice of semiconductor material used to fabricate integrated circuits or other microdevices1. Also called a slice or substrate, wafers must undergo a number of steps in the preparation process before they are ready for use.
Wafer Preparation: Front-end-of-line FEOL Processing
Front-end-of-line (FEOL) processing is the first series of steps in integrated circuit fabrication, involving the formation of transistors directly in silicon. Prior to the actual creation of the raw wafer itself, numerous steps can be taken to improve the performance of the resulting transistors, including processes to improve electronic mobility or reduce parasitic effects2. Raw wafers can be engineered by growing an ultrapure silicon layer via epitaxy (the deposition of an overlayer on a crystalline substrate, with the overlayer being in registry with the substrate3 ).
Individual devices, including transistors, capacitors, resistors, and more, are patterned into the semiconductor during FEOL processing, as well. The isolated transistors on the wafer are interconnected to produce the desired electrical circuits.4 Special wires isolated by dielectric layers are used to interconnect the individual devices.
To create these wires, a blanket film of aluminum or copper is deposited, then patterned and etched. The excess material is then removed, leaving isolated wires. In current FEOL practices, SiOC (silicon oxycarbide) materials, with dielectric constants of around 2.7, are generally used for the dielectric layer.
Multiple layers of interconnected devices can then be further interconnected by etching tiny holes in the insulating material and depositing tungsten or similar materials into these holes via chemical vapor deposition5. This step can be repeated as often as necessary to create a microchip with the necessary number of layers; however, though adding layers can potentially improve performance, it also reduces yield and increases manufacturing costs.
Back-end-of-line (BEOL) Wafer Processing
The second part of the IC fabrication progression is the back end of line (BEOL) process where individual devices such as transistors, capacitors, resistors, etc. are interconnected with the metalization wiring layer of the wafer. These processes include wafer backgrinding, wafer dicing, inspection, die sort and final packaging. The steps of the BEOL process include:
- Silicidation of source and drain regions and the polysilicon region.
- Adding a dielectric (first, lower layer is Pre-Metal dielectric, PMD – to isolate metal from silicon and polysilicon), CMP processing it
- Make holes in PMD, make a contacts in them.
- Add metal layer 1
- Add a second dielectric (this time it is Intra-Metal dielectric)
- Make vias through dielectric to connect lower metal with higher metal. Vias filled by Metal CVD process.
- Repeat steps 4–6 to get all metal layers.
- Add final passivation layer to protect the microchip.
Wafer Backgrinding / Wafer Thinning
Wafer backgrinding, also referred to as "backlap" or "wafer thinning," is a process in which the backside of a wafer is ground down, producing a thinner wafer that allows more layers and a higher density of integrated circuits to fit in a smaller package. Additional reasons for creating an ultra thin wafer may be for flexibility or heat dissipation reasons. Most silicon wafers are manufactured at roughly 750 μm thickness, but through backgrinding can be reduced to as little as 50 μm or less.
Prior to backgrinding, wafers typically undergo a thorough cleaning process and surface lamination. In the lamination stage, a protective tape is applied over the surface of the wafer to protect against mechanical damage and contamination by grinding fluid and debris6.
To support wafers during "ultra-thin" wafer grinding and other post-grinding operations, the 3M Wafer Support SystemTM is often employed. In this process, a UV-curable adhesive is applied to wafer surfaces and used as a bonding agent between glass support substrates and wafers. Grinding stresses on the wafer are minimized as the adhesive flows into and supports the topography of the circuit patterns on the front side of the wafers. After backgrinding and any post-grinding procedures, the glass substrates are removed via laser debonding7
Laminated wafers are then loaded into wafer cassettes, which in turn are loaded into an automated backgrinding machine. This machine uses a robotic arm to pick up the wafers and position them, back side facing up, under high precision, computer-controlled grinding wheels.
To achieve the ultra thin thicknesses or specific surface roughness requirements, multiple grind wheels may be employed, starting with a coarse grit and progressing to wheels with finer and finer grits8 . For the final surface finishing process, extremely fine diamond grit is often used.
To remove debris from wafers during the backgrinding process, a continuous wash of deionized water is employed. Additionally, to prevent contamination from external sources, backgrinding is commonly performed in cleanroom environments, generally Class 1,000 or better9 .
Other methods of thinning wafers are available, as well, including chemical and plasma etching processes. While these procedures are capable of producing even thinner wafers than backgrinding, they are generally more costly. Backgrinding remains the most popular and widely used wafer thinning method.
To produce even thinner wafers, thinner than 50 μm, two or more processes are often combined. The 3M Wafer Support SystemTM can be used in tandem with SEZ etch and/or CMP (chemical mechanical planarization) polishing for this purpose. SEZ etch and CMP polishing are wet chemical processes designed to gently remove silica material without placing additional mechanical stress on wafers.
After backgrinding, wafers must be diced to separate the individual silicon chips that are used in building electronic devices from the wafer itself. Wafer dicing can be achieved through scribing and breaking, by mechanical sawing, or by laser cutting. All methods are typically automated to ensure precision and accuracy.
The resulting cut pieces of wafer are referred to as die, dice, or dies. The die created may be of any shape with straight line edges, typically rectangles or squares. In rare instances, die will be cut in other, specialized shapes; this process must be performed with a laser dicer. Die generally range from 35 mm to 0.1 mm across, usually trending toward smaller end of measure.
In wafer dicing, the wafers are first mounted on dicing tape, similar to the tape used in backgrinding. This tape holds the wafer to a thin metal frame (saw frame) which supports it during the dicing process. The laser dicing process is an exception to this, as instead of a metal frame, the wafer is secured to an underlying carrier membrane that expands after the laser has made its cuts, inducing fracture and separating the dies10 .
After dicing, the die remain on the dicing tape until they are extracted by die sorting equipment. At this point, they are often packaged in waffle pack trays, Gel-Paks®,tape and reel packaging or placed directly onto printed circuit boards. Die used in this form are often referred to as "bare die". Other die may go through the full die attach, wire bonding and full integrated circuit assembly processes.
Wafer dies can also be separated without full dicing, using a process called "dice before grind." Here, wafers are pre-diced to a depth below the final required thickness. Then, the wafer is background as normal-backgrinding thins the wafer to beyond the pre-diced depth, leaving separate dies on the backgrinding tape.
Wafers can be inspected before or after the dicing process. Visual wafer inspection is used to remove visually defective die; that is die that fail specific criteria as set by various industry or manufacturer specifications. These defects may have been created during fabrication or by physical mishandling in post fab processes. Most visual inspections are carried out by fully automated equipment, though manual inspection processes are often utilized, as well. Automated inspection equipment can identify wafer defects as small as one micron11 .
Generally, wafers must meet certain industry specifications, depending on the intended final application of the wafer or die. Military-standard specifications, or mil-spec, are common, particularly MIL-STD-883. Many commercial and other less-stringent inspection requirements are also common.
While all die on a single wafer are intended to be identical, there are almost always a good percentage that do not meet standards. The individual die are categorized as passing or non-passing, with the information stored in an electronic wafer map; or, non-passing die may be marked with ink dots. Image capture may also be used to provide immediate feedback.
Essentially, die sorting is the process of removing known good die from a diced, electrical tested and visually inspected wafer and placing them into packaging, such as waffle packs, Gel-Paks®, or tape and reel, preparing them for further processing steps. The process of die sorting improves assembly and final product test yield and reduces overall manufacturing costs.
Die sorting can be performed manually, by automated equipment, or through a combination of both. Automated die sorting is commonly known as die pick, or die pick-and-place. These systems use automated visual die maps based on information gleaned during electrical test and wafer inspection to locate passing die; most are also capable of recognizing ink dot indicators, as well.
Our Die Sorting Solutions Offer:
- 3" to 8" wafer diameter capability
- Fast turnaround time to get your product ready for final assembly
- Pizza Mask and engineering projects
- Inverting capabilities for bumped devices
- A Large variety of pick tips and needle configurations in stock to handle various customer die sorting requirements
- Ink dot or wafer map input
- Embossed SMD tape and reel, Gel Pak®, and chip tray/waffle pack outputs
- Customized labeling.